Clock generating circuit

ABSTRACT

In a clock generation circuit generating a clock that is synchronized with a reference signal, it is an object to provide stable clocks by controlling phase jitter in a generated clock upon change of the reference signal, eliminate a stable-state phase difference between the reference signal and the generated clock so that control is eliminated, and allow the clock generation circuit to be integrated. The clock generation circuit is configured with multiple stages of PLL circuits such that PLL circuits  2  are provided for reference signals  1 , respectively, and one of outputs from the PLL circuits  2  is selected to be fed to a PLL circuit  5  provided in a next stage. The phase fluctuation of a signal inputted to the PLL circuit  5  upon change of the reference signal  1  is reduced to control the phase jitter of the generated clock  6 , thus allowing high loop gain in both the PLL circuit  2  and the PLL circuit  5 . Then, phase difference between the reference signal  1  and the generated clock  6  is eliminated to eliminate control involved, so that the clock generation circuit may be integrated.

TECHNICAL FIELD

This invention relates to a clock generation circuit, which generates aclock that is synchronized with a reference signal in a digitaltransmission system.

BACKGROUND ART

FIG. 9 is the block diagram of a conventional clock generation circuitas an example. With referring to the figure, a reference numeral 1denotes a reference signal, a reference numeral 3 denotes a selectionsignal selecting one of a plurality of reference signals, a referencenumeral 4 denotes a selection circuit, a reference numeral 5 denotes aPLL circuit, and a reference numeral 6 denotes a generated clock. ThePLL circuit is configured with the following elements. A referencenumeral 21 denotes a phase comparator, a reference numeral 22 denotes alow-pass filter, a reference numeral 23 denotes an amplifier, areference numeral 24 denotes a reference voltage generator, a referencenumeral 25 denotes a voltage control oscillator, and a reference numeral26 denotes a divider.

The operation is now described. A plurality of reference signals 1 areinputted, and one of the plurality of reference signals is selected inthe selection circuit 4 based on the selection signal 3. FIG. 9 showsthe case of inputting two reference signals 1 a and 1 b for explanation.Then, the phase of a selected reference signal land the phase of asignal outputted from the divider 26 are compared in the phasecomparator 21. The phase comparator 21 outputs a signal corresponding toa phase difference between the selected reference signal and the outputsignal from the divider 26. This phase difference signal is smoothedthrough the low-pass filter 22, and a voltage potential differencebetween this signal and the reference voltage generator 24 is amplifiedin the amplifier 23. The output voltage of the amplifier 23 activatesthe voltage control oscillator 25 to output the clock signal 6 whosephase is synchronized with the phase of the selected reference signal 1.The divider 26 divides the generated clock 6 to generate the signalwhose phase is to be compared with the phase of the reference signal 1.

FIG. 10 shows the reference signals 1, an output from the selectioncircuit 4 that is selected based on the selection signal 3, thegenerated clock 6, and an output signal from the divider 26. At 1001 inFIG. 10, it is illustrated that a reference signal 1 a is selected inthe selection circuit 4 based on the selection signal 3, and the divider26 and the generated clock 6 are both synchronized with the referencesignal 1 a.

With 1002 in FIG. 10, it is illustrated that a reference signal 1 b isselected upon change of the selection in the selection circuit 4 basedon the selection signal 3. In this state, the generated clock 6 and theoutput of the divider 26 are both out of phase with the reference signal1 b just selected. The phase comparator 21 outputs a phase differencesignal in commensurate with this phase difference. The phase differencesignal is then smoothed through the low-pass filter 22, and amplifiedthrough the amplifier 23 to control the transmission frequency of thevoltage control oscillator 25 so that the phase of the output of thedivider 26 and the phase of the reference signal 1 b selected in theselection circuit 4 match.

At 1003 in FIG. 10, it is illustrated that the generated clock 6 and theoutput of the divider 26 are both synchronized with the reference signal1 b changed through the circuit operation mentioned above.

With the conventional circuit, it is needed to control the referencevoltage generator 24 so as to match the phase of the selected referencesignal 1 and the phase of the generated clock 6. In steady state, phasedifference between the selected reference signal 1 and the generatedclock 6 is called steady-state phase difference. The phase differencemay be reduced by increasing the loop gain of the PLL circuit 5.However, the problem is that the transient phase fluctuation of thegenerated clock 6 gets large because it is affected by the change inphase of the reference signal 1 upon change of the reference signal 1.There is a tradeoff relation between the steady-state phase differenceand the size of the phase fluctuation of the generated clock 6 uponchange of the reference signal 1.

Further, it is hard to integrate the low-pass filter 22 for enhancingfilter precision performance because the low-pass filter 22 is generallyconfigured with such as a resistance and a capacitor. As the voltagecontrol oscillator 25, there is VCXO (Voltage Controlled XtalOscillator) using crystal or VCO (Voltage Controlled Oscillator) usingcoils and capacitors. It is difficult to integrate VCXO. With VCO, itsmodulation sensitivity is so high that loop gain gets high in the PLLcircuit. Therefore, the problem is that the phase fluctuation of thegenerated clock becomes large upon change of the reference signal.

The conventional clock generation circuit, thus configured, needs tocontrol the reference voltage generator for matching the phase of thereference signal and the phase of the generated clock. And there is aproblem that it is difficult to integrate the low-pass filter or thevoltage control oscillator in the case of high precision control of thesteady-state phase difference or the transient response upon change ofthe reference signal. Still another problem is that the transientresponse upon change of the reference signal depends upon loop gain inthe PLL circuit and the time constant of the low-pass filter, so thathigh design flexibility cannot be achieved.

The present invention is directed to solving the problems discussedabove. It is an object to eliminate control involved to match the phaseof the reference signal and the phase of the generated clock, make itpossible to integrate all the circuit elements, enable high precisiontransient response control upon change of the reference signal, andachieve high design flexibility.

DISCLOSURE OF THE INVENTION

A clock generation circuit according to the present invention selectsone of a plurality of reference signals and generates a clock that issynchronized with a selected reference signal. The clock generationcircuit is characterized by including,

(1) a plurality of former stage PLL circuits respectively provided foreach of the plurality of reference signals, generating outputs that arerespectively synchronized with a corresponding reference signal,

(2) a selection circuit selecting one of the outputs from the pluralityof former stage PLL circuits, and

(3) a latter stage PLL circuit linked in sequence to the plurality offormer stage PLL circuits, for receiving the one of the outputs selectedand generating the clock.

The clock generation circuit is characterized by further including aplurality of phase control circuits, respectively which is provided foreach of the outputs from the plurality of former stage PLL circuits formatching phase of an output from another one of the plurality of formerstage PLL circuits with the phase of an output from one of the pluralityof former stage PLL circuits corresponding to the selected referencesignal.

The phase control circuits are characterized by including a ring counterand a selection circuit selecting one of multiphase outputs from thering counter.

The plurality of former stage PLL circuits is characterized byrespectively performing synchronization in frequency with acorresponding reference signal, respectively.

The latter stage PLL circuit is characterized by performingsynchronization in phase with the selected reference signal.

The clock generation circuit is characterized by further including aplurality of phase control circuits respectively provided for each ofthe outputs from the plurality of former stage PLL circuits, andcontrolling a phase control circuit corresponding to the selectedreference signal such that the phase of a signal obtained by dividingthe generated clock matches the phase of the selected reference signal.

The plurality of phase control circuits are characterized by matchingthe phase of an output from another one of the plurality of former stagePLL circuits with the phase of an output from one of the plurality offormer stage PLL circuits corresponding to the selected referencesignal.

The clock generation circuit is characterized by controlling the phasecontrol circuit in commensurate with a cycle of the selected referencesignal.

The clock generation circuit is characterized by controlling the phasecontrol circuit in commensurate with a dividing cycle of the generatedclock.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a clock generation circuit according to afirst embodiment.

FIG. 2 shows a waveform of each element of the clock generation circuitaccording to the first embodiment.

FIG. 3 is a block diagram of a clock generation circuit according to asecond embodiment.

FIG. 4 is a block diagram of a phase control circuit according to athird embodiment.

FIG. 5 shows a waveform of each element of the phase control circuitaccording to the third embodiment.

FIG. 6 is a block diagram of a clock generation circuit according to afourth embodiment.

FIG. 7 is a block diagram of a clock generation circuit according to afifth embodiment.

FIG. 8 is a block diagram of a clock generation circuit according to asixth embodiment.

FIG. 9 is a block diagram of a conventional art clock generationcircuit.

FIG. 10 shows a wave form of each element of the conventional art clockgeneration circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1.

Hereinafter, a first embodiment is discussed with reference to FIG. 1.With referring to FIG. 1, a reference numeral 1 denotes a referencesignal, a reference numeral 2 denotes a PLL circuit, a reference numeral3 denotes a selection signal, a reference numeral 4 denotes a selectioncircuit, a reference numeral 5 denotes a PLL circuit, and a referencenumeral 6 denotes a generated clock. FIG. 2 shows the waveform of eachelement in FIG. 1.

As shown in FIG. 1, the reference signals 1 are inputted, respectively,to the PLL circuits 2. More specifically, a reference signal 1 a isinputted to a PLL circuit 2 a, and a reference signal 1 b is inputted toa PLL circuit 2 b. The PLL circuits 2 a and 2 b output primary clocksthat are synchronized, respectively, with the reference signals 1 a and1 b inputted.

Then, the selection circuit 4 selects one of the primary clocks that aresynchronized with the reference signals outputted from the PLL circuits2, respectively, based on the selection signal 3. A selected primaryclock is inputted to the PLL circuit 5 provided in the next stage ThePLL circuit 5 outputs the generated clock 6 that is synchronized withthe selected primary clock.

Reference numerals 201 and 202 in FIG. 2 each show the waveform of eachelement in the case where the reference signal 1 a is selected based onthe selection signal 3. At 201 in FIG. 2, it is illustrated that anoutput from the PLL circuit 2 a is synchronized with the referencesignal 1 a, an output from the PLL circuit 2 b is synchronized with thereference signal 1 b, and the reference signal 1 a is selected in theselection circuit 4 based on the selection signal 3. Consequently, thephase of the generated clock 6 is synchronized with the phase of thereference signal 1 a. At 202 in FIG. 2, it is illustrated that thereference signal 1 a is selected based on the selection signal 3 in theselection circuit 4. Therefore, the phase of the generated clock 6 isnot synchronized with the phase of the reference signal 1 b.

With 203 in FIG. 2, it shows the waveform of each element just after thereference signal was changed to the reference signal 1 b in theselection circuit 4 based on the selection signal 3. With this state,the output of the selection circuit 4 is synchronized with the referencesignal 1 b, but the PLL circuit is in a transient state tosynchronization with the reference signal 1 b just changed, and thegenerated clock 6 is not synchronized with the reference signal 1 b yet.

At 204 in FIG. 2, the waveform of each element in steady state is shownwith time. The phase of the generated clock 6 is synchronized with thephase of the reference signal 1 b selected in the selection circuit 4based on the selection signal 3.

According to the first embodiment, the PLL circuits 2 are provided forthe reference signals 1, respectively, and generate the primary clocksthat are synchronized with the respective reference signals 1. Then, oneof the primary clocks is selected and inputted to the PLL circuit 5 inthe next stage to obtain the generated clock 6. With the conventionalart, upon change of the reference signal 1 based on the selection signal3, phase difference between the reference signals 1 before and after thechange is inputted directly to the PLL circuit 5 generating the clock.According to this embodiment, however, phase difference between theprimary clocks before and after the change, which are outputted from thePLL circuits 2, is inputted to the PLL circuit 5 generating the clock.As shown in FIG. 2, to generate a more high-speed primary clock than thereference signal 1 makes it possible to reduce the phase differenceinputted to the PLL circuit 5 greatly upon change of the referencesignal 1. This results in allowing the phase fluctuation of thegenerated clock 6 that is outputted from the PLL circuit 5 to be reducedgreatly. Hence, stable clocks may be provided in a system.

The PLL circuits 2 are thus provided for the reference signals 1,respectively. This further contributes to eliminating phase jitter withthe input signal in each PLL circuit 2 upon change of the input signal.Accordingly, with respect to the problem of the setup of loop gain inthe PLL circuit, which is trade-off with the transient response by thephase jitter of the input signal, in the conventional art, the presentinvention allows high loop gain setting in the PLL circuit 2. This caneliminate the phase control that is essential in the conventional art.Likewise, in the PLL circuit 5, the phase jitter of the input signal isgreatly reduced, so that high loop gain may be obtained, thuseliminating phase control.

The phase jitter of the input signal thus greatly reduced in both thePLL circuit 2 and the PLL circuit 5 contributes not only to allowinghigh loop gain setting, but also to allowing a reduction in theprecision of transient response control. Consequently, it becomespossible to integrate the voltage control oscillator 25 or the low-passfilter 22, thus allowing apparatuses to be downsized and energyconsumption to be lowered.

According to the first embodiment, two types of the reference signals 1are inputted, as an example. The present invention is applicable toanother case in which more than two types of the reference signals 1 areto be inputted. Furthermore, two stages of the PLL circuits are linkedin sequence here as an example. It is also applicable, other than thisexample, that more than two stages of the PLL circuits are linked insequence.

Embodiment 2.

A second embodiment is now discussed with reference to the drawings.With referring to FIG. 3, a reference numeral 1 denotes a referencesignal, a reference numeral 2 denotes a PLL circuit (former stage), areference numeral 3 denotes a selection signal, a reference numeral 4denotes a selection circuit, a reference numeral 5 denotes a PLL circuit(latter stage), a reference numeral 6 denotes a generated clock, areference numeral 7 denotes a phase control circuit, a reference numeral8 denotes a phase comparator circuit, and a reference numeral 9 denotesa control circuit.

According to the second embodiment, the phase control circuits 7 areprovided, respectively, at the outputs of the PLL circuits 2 receivingthe reference signals 1, so that the phase of the primary clockoutputted from the phase control circuit 7 through the PLL circuit 2corresponding to the reference signal 1 selected in the selectioncircuit 4 based on the selection signal 3 and the phase of the primaryclock outputted from the phase control circuit 7 through the PLL circuit2 corresponding to the other reference signal 1 match. The phase of theprimary clock that is selected and the phase of the other primary clockare compared in the phase comparator circuit 8. The control circuit 9controls the phase control circuit that outputs the primary clock thatis not selected so that the phases of the both primary clocks match.

Thus, the phase of the primary clock that is not selected is controlledto match the phase of the primary clock that is selected. Consequently,no phase jitter occurs in the input signal that is inputted to the PLLcircuit 5 upon change in the selection circuit 4 based on the selectionsignal 3. This may provide more stable clocks, in addition to thebenefits of integration and elimination of control that are discussed inthe first embodiment

Embodiment 3.

According to a third embodiment, the phase control circuit 7 discussedin the second embodiment is implemented by a ring counter and aselection circuit.

With referring to FIG. 4, a reference numeral 1 denotes a referencesignal, a reference numeral 2 denotes a PLL circuit (former stage), areference numeral 7 denotes a phase control circuit, a reference numeral10 denotes flip-flops, a reference numeral 11 denotes a NOR circuit, areference numeral 12 denotes a selection circuit, a reference numeral 13denotes a control signal, and a reference numeral 14 denotes an outputof the phase control circuit. FIG. 5 shows the waveform of each elementin FIG. 4.

The primary clock outputted from the PLL circuit 2 operates a ringcounter that is configured with flip-flops 10 and the NOR circuit 11. Asshown in FIG. 5, outputs from a flip-flop 10 a˜a flip-flop 10 y aremulti-phase signals depending upon the number of the stages in the ringcounter. Selecting one of the multi-phase signals by using the selectioncircuit 12, configures the phase control circuit 7. The outputs from theflip-flop 10 a˜the flip-flop 10 y are cyclic. In the phase controloperation, if it is needed to control phase to delay further while theoutput of the flip-flop 10 y is selected by the selection circuit 12,the output of the flip-flop 10 a is to be selected by the selectioncircuit 12. As a phase control method for increasing or decreasing phaseslightly and serially, the outputs of the flip-flops 10 which isselected by the selection circuit 12, is to be selected by cyclically.This can make the range of phase control infinite in the phase controlcircuit 7.

The number of the flip-flops 10 making up the ring counter in the phasecontrol circuit 7 is determined in combination with the speed of theprimary clock outputted from the PLL circuit 2. More specifically, thenumber of stages of the flip-flops 10 is determined as resolution thatis necessary for phase control so that no phase jitter occurs in thegenerated clock 6 that is outputted from the PLL circuit 5 upon changein the selection circuit 4.

The phase control circuit 7 thus configured allows the range of phasecontrol to become infinite, thus allowing control resolution for phasecontrol to be set freely.

Embodiment 4.

According to a fourth embodiment, frequency-synchronization is carriedout with the reference signals in the PLL circuits 2 provided for therespective reference signals 1 as discussed in the first embodiment, oneof the frequency-synchronized signals is selected in the selectioncircuit 4, the selected signal is then inputted to the PLL circuit 5 inthe next stage, and phase-synchronization is carried out with theselected reference signal 1 in the PLL circuit 5 in the next stage.

With referring to FIG. 6, a reference numeral 1 denotes a referencesignal, a reference numeral 2 denotes a PLL circuit (former stage), areference numeral 3 denotes a selection signal, a reference numeral 4denotes a selection circuit, a reference numeral 5 denotes a PLL circuit(latter stage), a reference numeral 6 denotes a generated clock, areference numeral 7 denotes a phase control circuit, a reference numeral8 denotes a phase comparator circuit, a reference numeral 9 denotes acontrol circuit, a reference numeral 15 denotes a selection circuit, areference numeral 16 denotes a phase comparator circuit, a referencenumeral 17 denotes a control circuit, a reference numeral 18 denotes adivider circuit, a reference numeral 19 denotes a selection circuit, anda reference numeral 20 denotes a selection circuit.

Incoming reference signals 1 are inputted, respectively, to the PLLcircuits 2. The PLL circuits 2 output the primary clocks that aresynchronized in frequency with the respective reference signals 1inputted. The primary clocks are inputted to the selection circuit 4through the respective phase control circuits 7. Then, one of theinputted primary clocks is selected based on the selection signal 3 andfed into the PLL circuit 5. Then, the generated clock 6 is outputtedfrom the PLL circuit 5.

The reference signals 1 are also inputted to the selection circuit 15,and one of the reference signals 1 is selected based on the selectionsignal 3. The selection circuit 15 and the selection circuit 4 selectthe same type of reference signal 1 and synchronized primary clock infrequency. The phase comparator circuit 16 compares the phase of thereference signal 1 selected in the selection circuit 15 and the phase ofa signal obtained by dividing the generated clock 6 through the dividercircuit 18. A result of phase comparison is inputted to the controlcircuit 17 and used to control the phase control circuit 7 correspondingto the selected reference signal 1. The phase control circuit 7 matchesthe phase of the reference signal 1 and the phase of the divided signaloutputted from the divider circuit 18.

The phase comparator circuit 8 compares the phase of the primary clockoutputted from the PLL circuit 2 receiving the selected reference signal1 and the phase of the primary clock outputted from the PLL circuit 2receiving the other reference signal 1. A result of phase comparison isinputted to the control circuit 9 and used to control the phase controlcircuit 7 corresponding to the selected reference signal 1. The phasecontrol circuit 7 matches the phase of the primary clock correspondingto the selected reference signal 1 and the phase of the primary clockcorresponding to the other reference signal 1. The selection circuit 19and the selection circuit 20 select the control of the phase controlcircuit 7 corresponding to the selected reference signal 1 and thecontrol of the phase control circuit 7 corresponding to the otherreference signal 1, respectively, based on the selection signal 3.

Thus, the PLL circuit 2 in the first stage carries outfrequency-synchronization with the reference signal 1, and the PLLcircuit 5 in the next stage carries out phase-synchronization with theselected reference signal 1. This not only allows providing the systemwith the generated clock 6 whose frequency is synchronized with theselected reference signal 1 but also allows reproducing the phase thatmatches the selected reference signal 1. This is applicable to framephase signal, for example. Furthermore, the phase of the primary clockcorresponding to the selected reference signal 1 matches the phase ofthe primary clock corresponding to the other reference signal 1. Thiscauses no phase jitter in the signal inputted to the PLL circuit 5 uponchange of the reference signal 1 in the selection circuit 4 based on theselection signal 3. Hence, stable clocks may be provided.

Embodiment 5.

According to a fifth embodiment, the control circuit 17 and the controlcircuit 9 for controlling the phase control circuits 7 of the fourthembodiment are controlled in commensurate with the cycle of the selectedreference signal 1.

With referring to FIG. 7, a reference numeral 1 denotes a referencesignal, a reference numeral 2 denotes a PLL circuit (former stage), areference numeral 3 denotes a selection signal, a reference numeral 4denotes a selection circuit, a reference numeral 5 denotes a PLL circuit(latter stage), a reference numeral 6 denotes a generated clock, areference numeral 7 denotes a phase control circuit, a reference numeral8 denotes a phase comparator circuit, a reference numeral 9 denotes acontrol circuit, a reference numeral 15 denotes a selection circuit, areference numeral 16 denotes a phase comparator circuit, a referencenumeral 17 denotes a control circuit, a reference numeral 18 denotes adivider circuit, a reference numeral 19 denotes a selection circuit, anda reference numeral 20 denotes a selection circuit.

Control cycle determines the transient response upon change of thereference signal 1 to be selected based on the selection signal 3.Compared to the conventional art in which the transient response iscontrolled based on the frequency characteristic of the low-pass filter,high precision control is allowed according to the fifth embodiment.Furthermore, the possibility of the frequency response of the low-passfilter restricts the design flexibility of the transient response uponchange of the reference signal 1 according to the conventional art.According to the fifth embodiment, however, the control is based onlogic circuit processing, and therefore there is the advantage of highdesign flexibility.

Embodiment 6.

According to a sixth embodiment, the control circuit 17 and the controlcircuit 9 for controlling the phase control circuits 7 of the fourthembodiment are controlled in commensurate with the cycle of a signalobtained by dividing the generated clock 6 in the divider circuit 18.

With referring to FIG. 8, a reference numeral 1 denotes a referencesignal, a reference numeral 2 denotes a PLL circuit (former stage), areference numeral 3 denotes a selection signal, a reference numeral 4denotes a selection circuit, a reference numeral 5 denotes a PLL circuit(latter stage), a reference numeral 6 denotes a generated clock, areference numeral 7 denotes a phase control circuit, a reference numeral8 denotes a phase comparator circuit, a reference numeral 9 denotes acontrol circuit, a reference numeral 15 denotes a selection circuit, areference numeral 16 denotes a phase comparator circuit, a referencenumeral 17 denotes a control circuit, a reference numeral 18 denotes adivider circuit, a reference numeral 19 denotes a selection circuit, anda reference numeral 20 denotes a selection circuit.

Control cycle determines the transient response upon change of thereference signal 1 to be selected based on the selection signal 3.Compared to the conventional art in which the transient response iscontrolled based on the frequency characteristic of the low-pass filter,high precision control is allowed according to the sixth embodiment.Furthermore, the possibility of the frequency response of the low-passfilter restricts the design flexibility of the transient response uponchange of the reference signal 1 according to the conventional art.According to the sixth embodiment, however, the control is based onlogic circuit processing, and therefore there is the advantage of highdesign flexibility.

As aforementioned, the clock generation circuit according to thisinvention is thus configured with the multiple stages of the PLLcircuits, which are linked in sequence, such that the PLL circuits areprovided for incoming reference signals, respectively, and one of theoutputs of the PLL circuits receiving the respective reference signalsis selected to be fed to the PLL circuit in the next stage. In addition,the phase control circuits are thus provided at the outputs of the PLLcircuits provided for the respective reference signals, so that thephase of the output of the PLL circuit receiving the selected referencesignal and the phase of the output of the PLL circuit receiving theother reference signal match through the phase control circuit. Thephase control circuit is configured with the ring counter and theselection circuit selecting one of the multiphase outputs of the ringcounter. Furthermore, frequency-synchronization with the referencesignal is carried out in the PLL circuits provided for receiving therespective reference signals, one of the frequency-synchronized signalsis selected, and the selected signal is synchronized in phase with thereference signal in the PLL circuit in the next stage. Thus, the phasecontrol circuits are controlled in commensurate with the cycle of thereference signal or the generated clock signal.

INDUSTRIAL APPLICABILITY

Generating the more high-speed primary clock than the reference signal 1makes it possible to greatly reduce the phase difference received by thePLL circuit 5 upon change of the reference signal 1. Consequently, thisallows the phase fluctuation of the generated clock 6 that is outputtedfrom the PLL circuit 5 to be greatly reduced. Hence, stable clocks maybe provided in a system.

Furthermore, the configuration of PLL circuits 2 provided respectivelyfor the reference signals 1 allows no phase jitter of the input signalupon change in the PLL circuit 2. With respect to the problem of theloop gain setup of the PLL circuit which is in the trade-off relationwith the transient response caused by the phase jitter of the inputsignal, according to the conventional art, the loop gain of the PLLcircuit 2 is allowed to be set high according to this invention. Thiscan eliminate the phase control that is indispensable in theconventional art. Likewise, in the PLL circuit 5, since the phase jitterof the input signal is reduced greatly, high loop gain may be obtained,hence, the phase control may be eliminated.

The great reduction of the phase jitter of the input signal in both thePLL circuits 2 and the PLL circuit 5 not only allows the loop gain to beset high, but also allows the accuracy of transient response control tobe reduced. Consequently, it becomes possible to integrate the voltagecontrol oscillator 25 and the low-pass filter 22, thus allowingapparatuses to be downsized and power consumption to be lowered.

The phase of the primary clock that is not selected is controlled tomatch the phase of the primary clock that is selected. Consequently, nophase jitter occurs in the input signal that is inputted to the PLLcircuit 5 upon change in the selection circuit 4 based on the selectionsignal 3. This may provide more stable clocks, in addition to thebenefits of integration and elimination of control that are discussed inthe first embodiment

The phase control circuit 7 thus configured allows the range of phasecontrol to become infinite, thus allowing control resolution for phasecontrol to be set freely.

The PLL circuit 2 in the first stage carries outfrequency-synchronization with the reference signal 1, and the PLLcircuit 5 in the next stage carries out phase-synchronization with theselected reference signal 1. This not only allows providing the systemwith the generated clock 6 whose frequency is synchronized with theselected reference signal 1 but also allows reproducing the phase thatmatches the selected reference signal 1. This is applicable to framephase signal, for example. Furthermore, the phase of the primary clockcorresponding to the selected reference signal 1 matches the phase ofthe primary clock corresponding to the other reference signal 1. Thiscauses no phase jitter in the signal inputted to the PLL circuit 5 uponchange of the reference signal 1 in the selection circuit 4 based on theselection signal 3. Hence, stable clocks may be provided.

Compared to the conventional art in which the transient response iscontrolled based on the frequency characteristic of the low-pass filter,high precision control is allowed according to the fifth embodiment.Furthermore, the possibility of the frequency response of the low-passfilter restricts the design flexibility of the transient response uponchange of the reference signal 1 according to the conventional art.According to the fifth embodiment, however, the control is based onlogic circuit processing, and therefore there is the advantage of highdesign flexibility. Compared to the conventional art in which thetransient response is controlled based on the frequency characteristicof the low-pass filter, high precision control is allowed according tothe sixth embodiment. Furthermore, the possibility of the frequencyresponse of the low-pass filter restricts the design flexibility of thetransient response upon change of the reference signal 1 according tothe conventional art. According to the sixth embodiment, however, thecontrol is based on logic circuit processing, and therefore there is theadvantage of high design flexibility.

1. A clock generation circuit comprising: a plurality of former stagePLL circuits configured to receive a reference signal and to generate anoutput synchronized to the received reference signal; a plurality ofphase control circuits each configured to match a phase of an outputfrom a former stage PLL circuit in the plurality of former stage PLLcircuits to a phase of an output from another former stage PLL, andgenerate a phase matched output; a phase detector configured to comparesaid phase matched outputs to generate a control signal to said phasecontrol circuits; a selection circuit configured to select one of thephase matched outputs from the plurality of former stage PLL circuits;and a latter stage PLL circuit linked in sequence to the plurality offormer stage PLL circuits, and configured to receive the selected outputand generate a clock that is synchronized with the selected phasematched output.
 2. The clock generation circuit according to claim 1,wherein the phase control circuits each include a ring counter and aselection circuit configured to select a multiphase output from the ringcounter.
 3. The clock generation circuit according to claim 1, whereineach former stage PLL circuit performs synchronization in frequency withthe received reference signal, and wherein the latter stage PLL circuitperforms synchronization in phase with the selected reference signal,the clock generation circuit further comprising, a divider circuitconfigured to divide the generated clock and to output a divided signal,wherein the phase control circuit is further configured to match a phaseof the divided signal to a phase of the selected reference signal. 4.The clock generation circuit according to claim 3, wherein the phasecontrol circuit is controlled based on a cycle of the selected referencesignal.
 5. The clock generation circuit according to claim 3, whereinthe phase control circuit is controlled based on a divided cycle of thegenerated clock.
 6. A clock generation circuit which selects one of aplurality of reference signals and generates a clock that issynchronized with a selected reference signal, the clock generationcircuit comprising: a plurality of former stage PLL circuitsrespectively provided for each of the plurality of reference signals,generating outputs that are respectively synchronized with acorresponding reference signal; a plurality of phase control circuits,respectively provided for each of the outputs from the plurality offormer stage PLL circuits, for matching phase of an output from anotherone of the plurality of former stage PLL circuits with phase of anoutput from one of the plurality of former stage PLL circuits togenerate matched outputs; a phase detector configured to compare saidphase matched outputs to generate a control signal to said phase controlcircuits; a selection circuit selecting one of the phase matched outputsPLL circuits; and a latter stage PLL circuit linked in sequence to theplurality of former stage PLL circuits, for receiving the selected phasematched output and generating the clock.
 7. The clock generation circuitaccording to claim 6, wherein the phase control circuits each include aring counter and a selection circuit configured to select a multiphaseoutput from the ring counter.
 8. The clock generation circuit accordingto claim 6, wherein each former stage PLL circuit performssynchronization in frequency with the corresponding reference signal,and wherein the latter stage PLL circuit performs synchronization inphase with the selected reference signal, the clock generation circuitfurther comprising, a divider circuit configured to divide the generatedclock and to output a divided signal, wherein the phase control circuitis further configured to match a phase of the divided signal to a phaseof the selected reference signal.
 9. The clock generation circuitaccording to claim 8, wherein the phase control circuit is controlledbased on a cycle of the selected reference signal.
 10. The clockgeneration circuit according to claim 8, wherein the phase controlcircuit is controlled based on a divided cycle of the generated clock.